As the operating speed of microprocessors continues to increase, the current drawn by the microprocessor tends to escalate. Increasing current tends to amplify the power supply noise which may limit processor performance. High frequency power supply noise or “first droop” is generally proportional to the rate of change of current and is managed by using decoupling capacitors installed in the center of the “land” side of the package substrate at the location of a cavity in the socket on the motherboard. On the other hand, low frequency power supply noise or “third droop” is proportional to the current drawn by the microprocessor and is usually managed by minimizing the total path resistance from the voltage regulator (VR) on the board to the microprocessor die. However, typical die packaging arrangements tend to make it difficult to achieve this goal of minimizing the resistance without resorting to costly measures such as (a) increasing the number of layers in the package substrate; (b) increasing the thickness of the metal layers in the package substrate; (c) increasing the number of socket contacts; and/or (d) increasing the thickness of metal layers in the motherboard.